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IPPS
2008
IEEE
15 years 6 months ago
Intermediate checkpointing with conflicting access prediction in transactional memory systems
Transactional memory systems promise to reduce the burden of exposing thread-level parallelism in programs by relieving programmers from analyzing complex inter-thread dependences...
M. M. Waliullah, Per Stenström
PPOPP
2006
ACM
15 years 5 months ago
McRT-STM: a high performance software transactional memory system for a multi-core runtime
Applications need to become more concurrent to take advantage of the increased computational power provided by chip level multiprocessing. Programmers have traditionally managed t...
Bratin Saha, Ali-Reza Adl-Tabatabai, Richard L. Hu...
ACISICIS
2008
IEEE
15 years 6 months ago
Lessons Learned from Implementing WS-Coordination and WS-AtomicTransaction
This paper presents the design and implementation of a transaction service that complies with the WS-Coordination and WS-AtomicTransaction standards. Such service builds upon XAct...
Ivan Silva Neto, Francisco Reverbel
PODC
2010
ACM
15 years 1 months ago
Brief announcement: single-version permissive STM
We present a single-version STM that satisfies a practical notion of permissiveness: it never aborts read-only transactions, and it only aborts an update transaction due to anothe...
Hagit Attiya, Eshcar Hillel
ISCA
2006
IEEE
125views Hardware» more  ISCA 2006»
15 years 5 months ago
Architectural Semantics for Practical Transactional Memory
Transactional Memory (TM) simplifies parallel programming by allowing for parallel execution of atomic tasks. Thus far, TM systems have focused on implementing transactional stat...
Austen McDonald, JaeWoong Chung, Brian D. Carlstro...