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» On Two Problems of Nano-PLA Design
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ASPDAC
2000
ACM
159views Hardware» more  ASPDAC 2000»
15 years 10 months ago
Analytical minimization of half-perimeter wirelength
Global placement of hypergraphs is critical in the top-down placement of large timing-driven designs 10, 16 . Placement quality is evaluated in terms of the half-perimeter wirelen...
Andrew A. Kennings, Igor L. Markov
DAC
2000
ACM
15 years 10 months ago
Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability
—Chemical–mechanical polishing (CMP) is an enabling technique used in deep-submicrometer VLSI manufacturing to achieve long range oxide planarization. Post-CMP oxide topography...
Ruiqi Tian, D. F. Wong, Robert Boone
SIGCOMM
2000
ACM
15 years 10 months ago
SmartBridge: A scalable bridge architecture
As the number of hosts attached to a network increases beyond what can be connected by a single local area network (LAN), forwarding packets between hosts on different LANs become...
Thomas L. Rodeheffer, Chandramohan A. Thekkath, Da...
EH
1999
IEEE
179views Hardware» more  EH 1999»
15 years 10 months ago
Artificial Evolution of Active Filters: A Case Study
This article focuses on the application of artificial evolution to the synthesis of analog active filters. The main objective of this research is the achievement of a new class of...
Ricardo Salem Zebulum, Marco Aurélio Cavalc...
ICCAD
1999
IEEE
125views Hardware» more  ICCAD 1999»
15 years 10 months ago
Direct synthesis of timed asynchronous circuits
This paper presents a new method to synthesize timed asynchronous circuits directly from the specification without generating a state graph. The synthesis procedure begins with a ...
Sung Tae Jung, Chris J. Myers