187 search results - page 6 / 38 » On Using Efficient Test Sequences for BIST |
IOLTS
2000
IEEE
15 years 1 months ago
2000
IEEE
The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. A...
ET
2002
14 years 9 months ago
2002
In this paper we present a new reseeding technique for test-per-clock test pattern generation suitable for at-speed testing of circuits with random-pattern resistant faults. Our te...
ICCAD
2002
IEEE
15 years 6 months ago
2002
IEEE
We present a new method of built-in-self-test (BIST) for sequential circuits and system-on-a-chip (SOC) using characteristic faults and circuitspeciļ¬c spectral information in th...
64
Voted
ITC
2000
IEEE
15 years 1 months ago
2000
IEEE
1 The term "functional BIST" describes a test method to control functional modules so that they generate a deterministic test set, which targets structural faults within ...
ET
2002
14 years 9 months ago
2002
The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. A...