301 search results - page 14 / 61 » On bounding the delay of a critical path |
111
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ISQED
2005
IEEE
15 years 5 months ago
2005
IEEE
As technology continues to scale beyond 100nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional c...
CASES
2000
ACM
15 years 4 months ago
2000
ACM
This paper presents designs for parallel saturating multioperand adders. These adders have only a single carrypropagate adder on the critical delay path, yet produce the same resu...
100
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DAC
2006
ACM
15 years 3 months ago
2006
ACM
Statistical static timing analysis (SSTA) has been a popular research topic in recent years. A fundamental issue with applying SSTA in practice today is the lack of reliable and e...
119
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GLVLSI
2007
IEEE
15 years 6 months ago
2007
IEEE
We present new timing and congestion driven FPGA placement algorithms with minimal runtime overhead. By predicting the post-routing critical edges and estimating congestion accura...
117
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DAC
2004
ACM
16 years 24 days ago
2004
ACM
CT An efficient statistical timing analysis algorithm that can handle arbitrary (spatial and structural) causes of delay correlation is described. The algorithm derives the entire ...