Sciweavers

2658 search results - page 494 / 532
» On efficient balanced codes
Sort
View
CODES
2006
IEEE
15 years 10 months ago
Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications
The memory subsystem of a complex multiprocessor systemson-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as...
Ilya Issenin, Nikil Dutt
187
Voted
MMSEC
2006
ACM
231views Multimedia» more  MMSEC 2006»
15 years 10 months ago
JPEG2000-based secure image authentication
We present an efficient JPEG2000-based image authentication scheme, which is robust to JPEG compression and other allowed signal processing operations. Positive wavelet-based wate...
Mathias Schlauweg, Dima Pröfrock, Erika M&uum...
CODES
2005
IEEE
15 years 9 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
CODES
2005
IEEE
15 years 9 months ago
Memory access optimizations in instruction-set simulators
Design of programmable processors and embedded applications requires instruction-set simulators for early exploration and validation of candidate architectures. Interpretive simul...
Mehrdad Reshadi, Prabhat Mishra
RSP
2000
IEEE
156views Control Systems» more  RSP 2000»
15 years 8 months ago
Quasi-Static Scheduling of Reconfigurable Dataflow Graphs for DSP Systems
Dataflow programming has proven to be popular for representing applications in rapid prototyping tools for digital signal processing (DSP); however, existing dataflow design tools...
Bishnupriya Bhattacharya, Shuvra S. Bhattacharyya