112 search results - page 7 / 23 » On improving optimization effectiveness in interconnect-driv... |
96
Voted
DAC
1997
ACM
15 years 1 months ago
1997
ACM
We propose a methodology for applying gate-level logic transformations to optimize power in digital circuits. Statistically simulated[14] switching information, gate delays, signa...
GLVLSI
2009
IEEE
15 years 4 months ago
2009
IEEE
In the context of nanoscale networks-on-chip (NoCs), each link implementation solution is not just a specific synthesis optimization technique with local performance and power im...
101
Voted
DAC
2006
ACM
15 years 10 months ago
2006
ACM
In this paper we propose a new communication synthesis approach targeting systems with sequential communication media (SCM). Since SCMs require that the reading sequence and writi...
85
Voted
DATE
2007
IEEE
15 years 4 months ago
2007
IEEE
Loop unrolling is a well-known compiler optimization that can lead to significant performance improvements. When used in High Level Synthesis (HLS) unrolling can affect the contr...
FPGA
2009
ACM
15 years 4 months ago
2009
ACM
Reconfigurable high-performance computing systems (RHPC) have been attracting more and more attention over the past few years. RHPC systems are a promising solution for accelerati...