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» On modeling top-down VLSI design
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GLVLSI
2007
IEEE
154views VLSI» more  GLVLSI 2007»
15 years 8 months ago
Analyzing and modeling process balance for sub-threshold circuit design
Joseph F. Ryan, Jiajing Wang, Benton H. Calhoun
99
Voted
VLSID
2004
IEEE
89views VLSI» more  VLSID 2004»
16 years 2 months ago
Response Surface Modeling of 100nm CMOS Process Technology using Design of Experiment
H. C. Srinivasaiah, Navakanta Bhat
108
Voted
ICCAD
1994
IEEE
111views Hardware» more  ICCAD 1994»
15 years 6 months ago
On modeling top-down VLSI design
We present an improved data model that reflects the whole VLSI design process including bottom-up and topdown design phases. The kernel of the model is a static version concept th...
Bernd Schürmann, Joachim Altmeyer, Martin Sch...
84
Voted
ISCAS
1999
IEEE
101views Hardware» more  ISCAS 1999»
15 years 6 months ago
Modeling of accumulation MOS capacitors for analog design in digital VLSI processes
S. Pavan, Yannis P. Tsividis, K. Nagaraj
116
Voted
DAC
1994
ACM
15 years 6 months ago
Cost of Silicon Viewed from VLSI Design Perspective
- This paper provides an overview of design/test/CAD silicon cost-related issues. All major factors contributing to the rapid growth of manufacturing costs are explained and a simp...
Wojciech Maly