315 search results - page 37 / 63 » On reducing load store latencies of cache accesses |
MSWIM
2005
ACM
15 years 3 months ago
2005
ACM
We investigate the impact of power control on latency in wireless ad-hoc networks. If transmission power is increased, interference increases, thus reducing network capacity. A no...
ISCAS
2006
IEEE
15 years 3 months ago
2006
IEEE
Abstract— Shared memory is a common inter-processor communication paradigm for on-chip multiprocessor SoC (MPSoC) platforms. The latency overhead of switch-based interconnection ...
FPL
2009
Springer
15 years 2 months ago
2009
Springer
This paper advocates the use of 3D integration technology to stack a DRAM on top of an FPGA. The DRAM will store future FPGA contexts. A configuration is read from the DRAM into a...
IPPS
2003
IEEE
15 years 2 months ago
2003
IEEE
Our recent work on uniprocessor and single-node multiprocessor (SMP) active memory systems uses address remapping techniques in conjunction with extended cache coherence protocols...
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SIGCOMM
1998
ACM
15 years 1 months ago
1998
ACM
The rapid growth of the World Wide Web has caused serious performance degradation on the Internet. This paper o ers an end-to-end approach to improving Web performance by collecti...