96 search results - page 17 / 20 » On test coverage of path delay faults |
TCAD
2002
14 years 9 months ago
2002
A test pattern generator (TPG) for built-in self-test (BIST), which can reduce switching activity during test application, is proposed. The proposed TPG, called dual-speed LFSR (DS...
ICCAD
1995
IEEE
15 years 1 months ago
1995
IEEE
Implementing a built-in self-test by a "test per clock" scheme offers advantages concerning fault coverage, detection of delay faults, and test application time. Such a ...
DATE
2004
IEEE
15 years 1 months ago
2004
IEEE
This paper presents 3LSSD, a novel, easilyautomatable approach for scan insertion and ATPG of asynchronous circuits. 3LSSD inserts scan latches only into global circuit feedback p...
VTS
2008
IEEE
15 years 3 months ago
2008
IEEE
With increasing IC process variation and increased operating speed, it is more likely that even subtle defects will lead to the malfunctioning of a circuit. Various fault models, ...
SAC
2009
ACM
15 years 4 months ago
2009
ACM
Software developers use testing to gain and maintain confidence in the correctness of a software system. Automated reduction and prioritization techniques attempt to decrease the...