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158
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CLEIEJ
2010
15 years 2 months ago
3D-Via Driven Partitioning for 3D VLSI Integrated Circuits
A 3D circuit is the stacking of regular 2D circuits. The advances on the fabrication and packaging technologies allowed interconnecting stacked 2D circuits by using 3D vias. Howeve...
Sandro Sawicki, Gustavo Wilke, Marcelo O. Johann, ...
WACV
2005
IEEE
15 years 10 months ago
Temporal Synchronization of Video Sequences in Theory and in Practice
— In this work, we present a formalization of the video synchronization problem that exposes new variants of the problem that have been left unexplored to date. We also present a...
Anthony Whitehead, Robert Laganière, Prosen...
133
Voted
SAT
2007
Springer
126views Hardware» more  SAT 2007»
15 years 10 months ago
Sensor Deployment for Failure Diagnosis in Networked Aerial Robots: A Satisfiability-Based Approach
Unmanned aerial vehicles (UAVs) represent an important class of networked robotic applications that must be both highly dependable and autonomous. This paper addresses sensor deplo...
Fadi A. Aloul, Nagarajan Kandasamy
GD
2003
Springer
15 years 9 months ago
Three-Dimensional Grid Drawings with Sub-quadratic Volume
A three-dimensional grid drawing of a graph is a placement of the vertices at distinct points with integer coordinates, such that the straight line-segments representing the edges ...
Vida Dujmovic, David R. Wood
PLDI
1995
ACM
15 years 8 months ago
Interprocedural Partial Redundancy Elimination and its Application to Distributed Memory Compilation
Partial Redundancy Elimination PRE is a general scheme for suppressing partial redundancies which encompasses traditional optimizations like loop invariant code motion and redun...
Gagan Agrawal, Joel H. Saltz, Raja Das