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» On the Circuit Implementation Problem
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144
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ICCAD
1994
IEEE
117views Hardware» more  ICCAD 1994»
15 years 7 months ago
Optimization of critical paths in circuits with level-sensitive latches
A simple extension of the critical path method is presented which allows more accurate optimization of circuits with level-sensitive latches. The extended formulation provides a s...
Timothy M. Burks, Karem A. Sakallah
ICCD
2007
IEEE
190views Hardware» more  ICCD 2007»
16 years 20 days ago
Hybrid resistor/FET-logic demultiplexer architecture design for hybrid CMOS/nanodevice circuits
Hybrid nanoelectronics are emerging as one viable option to sustain the Moore’s Law after the CMOS scaling limit is reached. One main design challenge in hybrid nanoelectronics ...
Shu Li, Tong Zhang
ICCAD
2008
IEEE
117views Hardware» more  ICCAD 2008»
15 years 10 months ago
A novel sequential circuit optimization with clock gating logic
— To save power consumption, it has been shown that the clock signal can be gated without changing the functionality under certain clock-gating conditions. We observe that the cl...
Yu-Min Kuo, Shih-Hung Weng, Shih-Chieh Chang
CCECE
2006
IEEE
15 years 9 months ago
Linearization Techniques for Cross-Coupled Transconductor Circuits Used in Integrated Q-Enhanced LC Filters
Integrated Q-enhanced RF LC filters using negative resistances implemented using cross coupled pairs frequently suffer from poor linearity performance. Several linearization met...
Holly Pekau, Jim Kulyk, James W. Haslett, Leonid B...
132
Voted
ISQED
2006
IEEE
106views Hardware» more  ISQED 2006»
15 years 9 months ago
Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration
We propose an accurate architecture-level power estimation method for SRAM memories. This hybrid method is composed of an analytical part for dynamic power estimation and a circui...
Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-...