10718 search results - page 196 / 2144 » On the Circuit Implementation Problem |
143
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VLSID
2001
IEEE
16 years 4 months ago
2001
IEEE
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
155
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FPGA
1998
ACM
15 years 8 months ago
1998
ACM
It has become clear that large embedded con gurable memory arrays will be essential in future FPGAs. Embedded arrays provide high-density high-speed implementations of the storage...
145
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AAAI
1996
15 years 5 months ago
1996
In this paper we describe the design and implementation of the derivation replay framework, dersnlp+ebl (Derivational snlp+ebl), which is based within a partial order planner. der...
135
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DDECS
2009
IEEE
15 years 11 months ago
2009
IEEE
—Quasi Delay Insensitive asynchronous logic is a very robust system allowing safe implementations while requiring minimal timing assumptions. Unfortunately the design methodologi...
151
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ASIAMS
2008
IEEE
15 years 10 months ago
2008
IEEE
A carry-select adder(CSA) can be implemented by using single ripple carry adder and an add-one circuit instead of using dual ripple-carry adders to reduce the area and power but w...