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» On the Circuit Implementation Problem
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FPGA
1997
ACM
145views FPGA» more  FPGA 1997»
15 years 1 months ago
Generation of Synthetic Sequential Benchmark Circuits
Programmable logic architectures increase in capacity before commercial circuits are designed for them, yielding a distinct problem for FPGA vendors: how to test and evaluate the ...
Michael D. Hutton, Jonathan Rose, Derek G. Corneil
ICCAD
1994
IEEE
131views Hardware» more  ICCAD 1994»
15 years 1 months ago
Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs
We consider the problem of performance driven lookup-table (LUT) based technology mapping for FPGAs using a general delay model. In the general delay model, each interconnection e...
Hannah Honghua Yang, D. F. Wong
ASPDAC
2001
ACM
107views Hardware» more  ASPDAC 2001»
15 years 1 months ago
An efficient solution to the storage correspondence problem for large sequential circuits
Abstract- Traditional state-traversal-basedmethods for verifying sequential circuits are computationally infeasible for circuits with a large number of memory elements. However, if...
Wanlin Cao, D. M. H. Walker, Rajarshi Mukherjee
IPCO
2007
81views Optimization» more  IPCO 2007»
14 years 11 months ago
Matching Problems in Polymatroids Without Double Circuits
According to the present state of the theory of the matroid matching problem, the existence of a good characterization to the size of a maximum matching depends on the behavior of ...
Márton Makai, Gyula Pap, Jácint Szab...
ICCAD
2004
IEEE
123views Hardware» more  ICCAD 2004»
15 years 6 months ago
Logical effort based technology mapping
We propose a new approach to library-based technology mapping, based on the method of logical effort. Our algorithm is close to optimal for fanout-free circuits, and is extended t...
Shrirang K. Karandikar, Sachin S. Sapatnekar