Abstract—This article discusses system-level techniques to optimize the power-performance trade-off in subthreshold circuits and presents a uniform platform for implementing ultr...
This paper presents a new design assistant for analog integrated circuits. The interactive tool is implemented in the Design Framework II of Cadence and supports the designer d...
Abstract: We describe a technique to estimate the energy consumed by speed-independent asynchronous (clockless) control circuits. Because speed-independent circuits are hazard-free...
Peter A. Beerel, Cheng-Ta Hsieh, Suhrid A. Wadekar
Previous work has shown that circuit representations can be exploited in QBF solvers to obtain useful performance improvements. In this paper we examine some additional techniques ...
This paper introduces a CAD framework for co-simulation of hybrid circuits containing CMOS and SET (Single Electron Transistor) devices. An improved analytical model for SET is al...