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» On the Circuit Implementation Problem
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113
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GECCO
2007
Springer
138views Optimization» more  GECCO 2007»
15 years 9 months ago
Reducing the number of transistors in digital circuits using gate-level evolutionary design
This paper shows that the evolutionary design of digital circuits which is conducted at the gate level is able to produce human-competitive circuits at the transistor level. In ad...
Zbysek Gajda, Lukás Sekanina
ASYNC
2004
IEEE
98views Hardware» more  ASYNC 2004»
15 years 7 months ago
Synthesis of Speed Independent Circuits Based on Decomposition
This paper presents a decomposition method for speedindependent circuit design that is capable of significantly reducing the cost of synthesis. In particular, this method synthesi...
Tomohiro Yoneda, Hiroomi Onda, Chris J. Myers
134
Voted
ICCAD
2001
IEEE
106views Hardware» more  ICCAD 2001»
16 years 10 days ago
A Layout-Aware Synthesis Methodology for RF Circuits
In this paper a layout-aware RF synthesis methodology is presented. The methodology combines the power of a differential evolution algorithm with cost function response modeling a...
Peter J. Vancorenland, Geert Van der Plas, Michiel...
DFT
2008
IEEE
149views VLSI» more  DFT 2008»
15 years 5 months ago
Can Knowledge Regarding the Presence of Countermeasures Against Fault Attacks Simplify Power Attacks on Cryptographic Devices?
Side-channel attacks are nowadays a serious concern when implementing cryptographic algorithms. Powerful ways for gaining information about the secret key as well as various count...
Francesco Regazzoni, Thomas Eisenbarth, Luca Breve...
123
Voted
ISLPED
2004
ACM
153views Hardware» more  ISLPED 2004»
15 years 8 months ago
Any-time probabilistic switching model using bayesian networks
Modeling and estimation of switching activities remain to be important problems in low-power design and fault analysis. A probabilistic Bayesian Network based switching model can ...
Shiva Shankar Ramani, Sanjukta Bhanja