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» On the Circuit Implementation Problem
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CCECE
2009
IEEE
15 years 10 months ago
An ultra compact block cipher for serialized architecture implementations
In this paper, we present a new block cipher, referred as PUFFIN2, that is designed to be used with applications requiring very low circuit area. PUFFIN2 is designed to be impleme...
Cheng Wang, Howard M. Heys
137
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DFT
2006
IEEE
82views VLSI» more  DFT 2006»
15 years 9 months ago
VLSI Implementation of a Fault-Tolerant Distributed Clock Generation
In this paper we will introduce a novel approach for the on-chip generation of a faulttolerant clock. We will motivate why it becomes more and more desirable to provide VLSI circu...
Markus Ferringer, Gottfried Fuchs, Andreas Steinin...
PATMOS
2005
Springer
15 years 9 months ago
Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing
Early circuit performance estimation and easy-to-apply methods for minimum-delay gate sizing are needed, in order to enhance circuit’s performance and to increase designers’ pr...
Giorgos Dimitrakopoulos, Dimitris Nikolos
141
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ICCAD
2003
IEEE
135views Hardware» more  ICCAD 2003»
15 years 8 months ago
ATPG for Noise-Induced Switch Failures in Domino Logic
Domino circuits have been used in most modern high-performance microprocessor designs because of their high speed, low transistor-count and hazard-free operation. However, with te...
Rahul Kundu, R. D. (Shawn) Blanton
ISCAS
2002
IEEE
91views Hardware» more  ISCAS 2002»
15 years 8 months ago
Efficient digit-serial FIR filters with skew-tolerant domino
A novel connection between digit-serialcomputationand skew-tolerant domino circuit design is exploited to create very efficient implementations of FIR digital filters. In our ap...
Sungwook Kim, Gerald E. Sobelman