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ARCS
2006
Springer
15 years 1 months ago
Fault-Tolerant Time-Triggered Ethernet Configuration with Star Topology
: We have shown in our past work that the standard configuration of Time-Triggered (TT) Ethernet unifies real-time and non-real-time traffic within a single coherent communication ...
Astrit Ademaj, Hermann Kopetz, Petr Grillinger, Kl...
TC
2011
14 years 4 months ago
An Architecture for Fault-Tolerant Computation with Stochastic Logic
—Mounting concerns over variability, defects and noise motivate a new approach for digital circuitry: stochastic logic, that is to say, logic that operates on probabilistic signa...
Weikang Qian, Xin Li, Marc D. Riedel, Kia Bazargan...
PROMISE
2010
14 years 4 months ago
Programmer-based fault prediction
Background: Previous research has provided evidence that a combination of static code metrics and software history metrics can be used to predict with surprising success which fil...
Thomas J. Ostrand, Elaine J. Weyuker, Robert M. Be...
SOSP
2001
ACM
15 years 6 months ago
BASE: Using Abstraction to Improve Fault Tolerance
ing Abstraction to Improve Fault Tolerance MIGUEL CASTRO Microsoft Research and RODRIGO RODRIGUES and BARBARA LISKOV MIT Laboratory for Computer Science Software errors are a major...
Rodrigo Rodrigues, Miguel Castro, Barbara Liskov
IOLTS
2006
IEEE
84views Hardware» more  IOLTS 2006»
15 years 3 months ago
Fault Tolerant System Design Method Based on Self-Checking Circuits
This paper describes a highly reliable digital circuit design method based on totally self checking blocks implemented in FPGAs. The bases of the self checking blocks are parity p...
Pavel Kubalík, Petr Fiser, Hana Kubatova