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» On the Implementation of Dynamic Patterns
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CODES
2007
IEEE
15 years 10 months ago
Predator: a predictable SDRAM memory controller
Memory requirements of intellectual property components (IP) in contemporary multi-processor systems-on-chip are increasing. Large high-speed external memories, such as DDR2 SDRAM...
Benny Akesson, Kees Goossens, Markus Ringhofer
HICSS
2007
IEEE
135views Biometrics» more  HICSS 2007»
15 years 10 months ago
Framework for Establishing Enterprise Modeling in the Context of Collaborative Enterprises
Increased market dynamics, shorter product lifecycles and a higher customer involvement in product design have caused great changes to competitive conditions and many companies ar...
Thomas Knothe, Timo Kahl, Dieter Boell, Kristof Sc...
IPPS
2007
IEEE
15 years 10 months ago
Formal Analysis for Debugging and Performance Optimization of MPI
High-end computing is universally recognized to be a strategic tool for leadership in science and technology. A significant portion of high-end computing is conducted on clusters...
Ganesh Gopalakrishnan, Robert M. Kirby
126
Voted
ISCA
2007
IEEE
145views Hardware» more  ISCA 2007»
15 years 10 months ago
Mechanisms for store-wait-free multiprocessors
Store misses cause significant delays in shared-memory multiprocessors because of limited store buffering and ordering constraints required for proper synchronization. Today, prog...
Thomas F. Wenisch, Anastassia Ailamaki, Babak Fals...
ISCAS
2007
IEEE
180views Hardware» more  ISCAS 2007»
15 years 10 months ago
Characterization of a Fault-tolerant NoC Router
— With increasing reliability concerns for current and next generation VLSI technologies, fault-tolerance is fast becoming an integral part of system-on-chip (SoC) and multicore ...
Sumit D. Mediratta, Jeffrey T. Draper
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