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» On the Inertia of the Asynchronous Circuits
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ASYNC
2007
IEEE
132views Hardware» more  ASYNC 2007»
15 years 3 months ago
Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis
Future deep sub-micron technologies will be characterized by large parametric variations, which could make asynchronous design an attractive solution for use on large scale. Howev...
Tiberiu Chelcea, Girish Venkataramani, Seth Copen ...
DATE
2003
IEEE
123views Hardware» more  DATE 2003»
15 years 2 months ago
XBM2PLA: A Flexible Synthesis Tool for Extended Burst Mode Machines
This paper describes the results of a new synthesis tool (XBM2PLA) for asynchronous state machines [2]. XBM2PLA generates the boolean functions for an asynchronous circuit. XBM2PL...
Oliver Kraus, Martin Padeffke
ICCAD
2003
IEEE
115views Hardware» more  ICCAD 2003»
15 years 6 months ago
Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits
This paper presents an efficient method for verifying hazard freedom in timed asynchronous circuits. Timed circuits are a class of asynchronous circuits that utilize explicit tim...
Curtis A. Nelson, Chris J. Myers, Tomohiro Yoneda
CORR
2006
Springer
90views Education» more  CORR 2006»
14 years 9 months ago
Relatively inertial delays
The paper studies the relatively inertial delays that represent one of the most important concepts in the modeling of the asynchronous circuits.
Serban E. Vlad
DAC
1996
ACM
15 years 1 months ago
A Technique for Synthesizing Distributed Burst-mode Circuits
We offer a technique to partition a centralized control-flow graph to obtain distributed control in the context of asynchronous highlevel synthesis. The technique targets Huffman-...
Prabhakar Kudva, Ganesh Gopalakrishnan, Hans M. Ja...