548 search results - page 29 / 110 » On the Limitations of Power Macromodeling Techniques |
126
click to vote
CODES
2004
IEEE
15 years 2 months ago
2004
IEEE
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...
ICCD
2007
IEEE
15 years 8 months ago
2007
IEEE
We present new techniques for explicit constraint satisfaction in the incremental placement process. Our algorithm employs a Lagrangian Relaxation (LR) type approach in the analyt...
88
Voted
ICPR
2006
IEEE
16 years 7 days ago
2006
IEEE
Numerous techniques exist which can be used for the task of behavioural analysis and recognition. Common amongst these are Bayesian networks and Hidden Markov Models. Although the...
103
Voted
CASES
2006
ACM
15 years 5 months ago
2006
ACM
Dynamic voltage scaling and sleep state control have been shown to be extremely effective in reducing energy consumption in CMOS circuits. Though plenty of research papers have st...
SAMOS
2004
Springer
15 years 4 months ago
2004
Springer
— Architectural resources and program recurrences are the main limitations to the amount of Instruction-Level Parallelism (ILP) exploitable from loops, the most time-consuming pa...