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» On the Theory of Stochastic Processors
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IEEEPACT
2008
IEEE
15 years 4 months ago
Leveraging on-chip networks for data cache migration in chip multiprocessors
Recently, chip multiprocessors (CMPs) have arisen as the de facto design for modern high-performance processors, with increasing core counts. An important property of CMPs is that...
Noel Eisley, Li-Shiuan Peh, Li Shang
ICS
2007
Tsinghua U.
15 years 3 months ago
Optimization of data prefetch helper threads with path-expression based statistical modeling
This paper investigates helper threads that improve performance by prefetching data on behalf of an application’s main thread. The focus is data prefetch helper threads that lac...
Tor M. Aamodt, Paul Chow
IPSN
2007
Springer
15 years 3 months ago
A compact, high-speed, wearable sensor network for biomotion capture and interactive media
In this paper, we present a wireless sensor platform designed for processing multipoint human motion with low latency and high resolution. One application considered here is inter...
Ryan Aylward, Joseph A. Paradiso
LCTRTS
2007
Springer
15 years 3 months ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...
IEEEPACT
2006
IEEE
15 years 3 months ago
An empirical evaluation of chains of recurrences for array dependence testing
Code restructuring compilers rely heavily on program analysis techniques to automatically detect data dependences between program statements. Dependences between statement instanc...
Johnnie Birch, Robert A. van Engelen, Kyle A. Gall...