3742 search results - page 45 / 749 » On the Use of Formal Techniques for Validation |
ICECCS
2002
IEEE
15 years 4 months ago
2002
IEEE
Distributed Java applications represent a large growth area in software. Validating such applications using information from runtime interactions is a challenge. We propose techni...
IJIT
2004
15 years 1 months ago
2004
As computer network technology becomes increasingly complex, it becomes necessary to place greater requirements on the validity of developing standards and the resulting technology...
103
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DATE
2004
IEEE
15 years 3 months ago
2004
IEEE
Formal verification techniques have been playing an important role in pre-silicon validation processes. One of the most important points considered in performing formal verificati...
126
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SAS
2012
Springer
13 years 2 months ago
2012
Springer
Abstract. Shivers’s escape technique enables one to analyse the control flow of higher-order program fragments. It is widely used, but its soundness has never been proven. In th...
DSD
2004
IEEE
15 years 3 months ago
2004
IEEE
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current Systemon-Chip design metho...