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» On the Use of Formal Techniques for Validation
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ASPDAC
2004
ACM
94views Hardware» more  ASPDAC 2004»
15 years 3 months ago
Improving simulation-based verification by means of formal methods
The design of complex systems is largely ruled by the time needed for verification. Even though formal methods can provide higher reliability, in practice often simulation based ve...
Görschwin Fey, Rolf Drechsler
RECOMB
2008
Springer
16 years 4 days ago
Internal Validation of Ancestral Gene Order Reconstruction in Angiosperm Phylogeny
Abstract. Whole genome doubling (WGD), a frequent occurrence during the evolution of the angiopsperms, complicates ancestral gene order reconstruction due to the multiplicity of so...
David Sankoff, Chunfang Zheng, P. Kerr Wall, Claud...
RSP
2005
IEEE
107views Control Systems» more  RSP 2005»
15 years 5 months ago
Rapid Prototyping of Embedded Software Using Selective Formalism
Our software synthesis tool, CSP++, generates C++ source code from verifiable CSPm specifications, and includes a framework for runtime execution. Our technique of selective for...
John D. Carter, Ming Xu, William B. Gardner
JSA
2008
131views more  JSA 2008»
14 years 11 months ago
Formal verification of ASMs using MDGs
We present a framework for the formal verification of abstract state machine (ASM) designs using the multiway decision graphs (MDG) tool. ASM is a state based language for describ...
Amjad Gawanmeh, Sofiène Tahar, Kirsten Wint...
APSEC
2004
IEEE
15 years 3 months ago
An Approach to Detecting Domain Errors Using Formal Specification-Based Testing
Domain testing, a technique for testing software or portions of software dominated by numerical processing, is intended to detect domain errors that usually arise from incorrect i...
Yuting Chen, Shaoying Liu