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DAC
2003
ACM
15 years 11 months ago
Clock-tree power optimization based on RTL clock-gating
As power consumption of the clock tree in modern VLSI designs tends to dominate, measures must be taken to keep it under control. This paper introduces an approach for reducing cl...
Monica Donno, Alessandro Ivaldi, Luca Benini, Enri...
DAC
2005
ACM
15 years 11 months ago
Power optimal dual-Vdd buffered tree considering buffer stations and blockages
This paper presents the first in-depth study on applying dual Vdd buffers to buffer insertion and multi-sink buffered tree construction for power minimization under delay constrai...
King Ho Tam, Lei He
VLSID
2009
IEEE
170views VLSI» more  VLSID 2009»
15 years 10 months ago
Code Transformations for TLB Power Reduction
The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB...
Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivasta...
VLSID
2006
IEEE
148views VLSI» more  VLSID 2006»
15 years 10 months ago
Efficient Design and Analysis of Robust Power Distribution Meshes
With increasing design complexity, as well as continued scaling of supplies, the design and analysis of power/ground distribution networks poses a difficult problem in modern IC d...
Puneet Gupta, Andrew B. Kahng
MOBISYS
2005
ACM
15 years 9 months ago
Turducken: hierarchical power management for mobile devices
Abstract-Maintaining optimal consistency in a distributed system requires that nodes be always-on to synchronize information. Unfortunately, mobile devices such as laptops do not h...
Jacob Sorber, Nilanjan Banerjee, Mark D. Corner, S...