195 search results - page 37 / 39 » On the energy-efficiency of software transactional memory |
108
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ISCA
2012
IEEE
13 years 1 days ago
2012
IEEE
Hybrid processors are HW/SW co-designed processors that leverage blocked-execution, the execution of regions of instructions as atomic blocks, to facilitate aggressive speculative...
ISPASS
2007
IEEE
15 years 3 months ago
2007
IEEE
This paper proposes the use of microprocessor performance counters for online measurement of complete system power consumption. While past studies have demonstrated the use of per...
92
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LCTRTS
2010
Springer
15 years 4 months ago
2010
Springer
With increasingly more complex Multi-Processor Systems on Chip (MPSoC) and shortening time-to- market projections, Transaction Level Modeling and Platform Aware Design are seen as...
DTJ
1998
14 years 9 months ago
1998
ir increasing use of abstraction, modularity, delayed binding, polymorphism, and source reuse, especially when these attributes are used in combination. Modern processor architectu...
103
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FPGA
2007
ACM
15 years 3 months ago
2007
ACM
Chip-multiprocessors are quickly gaining momentum in all segments of computing. However, the practical success of CMPs strongly depends on addressing the difficulty of multithread...