Sciweavers

191 search results - page 8 / 39
» On-Chip Communication Architecture for OC-768 Network Proces...
Sort
View
CODES
2003
IEEE
15 years 5 months ago
A modular simulation framework for architectural exploration of on-chip interconnection networks
Ever increasing complexity and heterogeneity of SoC platforms require diversified on-chip communication schemes beyond the currently omnipresent shared bus architectures. To prev...
Tim Kogel, Malte Doerper, Andreas Wieferink, Raine...
ISCA
2009
IEEE
186views Hardware» more  ISCA 2009»
15 years 6 months ago
Application-aware deadlock-free oblivious routing
Conventional oblivious routing algorithms are either not application-aware or assume that each flow has its own private channel to ensure deadlock avoidance. We present a framewo...
Michel A. Kinsy, Myong Hyon Cho, Tina Wen, G. Edwa...
ANCS
2009
ACM
14 years 9 months ago
EINIC: an architecture for high bandwidth network I/O on multi-core processors
This paper proposes a new server architecture EINIC (Enhanced Integrated NIC) for multi-core processors to tackle the mismatch between network speed and host computational capacit...
Guangdeng Liao, Laxmi N. Bhuyan, Danhua Guo, Steve...
COMPCON
1996
IEEE
15 years 3 months ago
Architecture of a Broadband MediaProcessor
A broadband mediaprocessor is a general-purpose computer system which reaches the goal of communicating and processing at broadband rates using compiled software rather than speci...
Craig Hansen
JSS
2006
104views more  JSS 2006»
14 years 11 months ago
Modelling and simulation of off-chip communication architectures for high-speed packet processors
In this work, we propose a visual, custom-designed, event-driven interconnect simulation framework to evaluate the performance of off-chip multi-processor/memory communications ar...
Jacob Engel, Daniel Lacks, Taskin Koçak