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VLSID
2008
IEEE
138views VLSI» more  VLSID 2008»
14 years 6 months ago
Memory Architecture Exploration Framework for Cache Based Embedded SOC
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...
DAC
2011
ACM
12 years 6 months ago
EFFEX: an embedded processor for computer vision based feature extraction
The deployment of computer vision algorithms in mobile applications is growing at a rapid pace. A primary component of the computer vision software pipeline is feature extraction,...
Jason Clemons, Andrew Jones, Robert Perricone, Sil...
ISCA
2009
IEEE
189views Hardware» more  ISCA 2009»
14 years 28 days ago
Hybrid cache architecture with disparate memory technologies
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ra...
DATE
2006
IEEE
159views Hardware» more  DATE 2006»
14 years 10 days ago
Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors
Reduced energy consumption is one of the most important design goals for embedded application domains like wireless, multimedia and biomedical. Instruction memory hierarchy has be...
Praveen Raghavan, Andy Lambrechts, Murali Jayapala...
ISCAPDCS
2001
13 years 7 months ago
Performance Evaluation of a Non-Blocking Multithreaded Architecture for Embedded, Real-Time and DSP Applications
This paper presents the evaluation of a non-blocking, decoupled memory/execution, multithreaded architecture known as the Scheduled Dataflow (SDF). The major recent trend in digit...
Krishna M. Kavi, Joseph Arul, Roberto Giorgi