704 search results - page 12 / 141 » On-chip logic minimization |
ASYNC
1998
IEEE
15 years 2 months ago
1998
IEEE
None of the available minimizers for exact 2-level hazard-free logic minimization can synthesize very large circuits. This limitation has forced researchers to resort to heuristic...
ICCD
2003
IEEE
15 years 6 months ago
2003
IEEE
This paper introduces a new method for two-level logic minimization. Unlike previous approaches, the new method uses a SAT solver as an underlying engine. While the overall minimi...
DAC
1996
ACM
15 years 1 months ago
1996
ACM
-- We present a new heuristic algorithm for hazard-free minimization of two-level logic. On nearly all examples, the algorithm finds an exactly minimum-cost cover. It also solves s...
DAC
2002
ACM
15 years 10 months ago
2002
ACM
105
click to vote
IJCAI
2003
14 years 11 months ago
2003
We consider the problem of updating nonmonotonic knowledge bases represented by epistemic logic programs where disjunctive information and notions of knowledge and beliefs can be ...