704 search results - page 21 / 141 » On-chip logic minimization |
ACS
2008
14 years 10 months ago
2008
Abstract. We define an out-degree for F-coalgebras and show that the coalgebras of outdegree at most form a covariety. As a subcategory of all Fcoalgebras, this class has a termin...
ISMVL
1999
IEEE
15 years 2 months ago
1999
IEEE
This paper considers an optimization method of programmable logic arrays (PLAs), which have two-input EXOR gate at the outputs. The PLA realizes an EXOR of two sum-of-products exp...
VTS
2002
IEEE
15 years 2 months ago
2002
IEEE
Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test v...
ITC
1999
IEEE
15 years 2 months ago
1999
IEEE
Power consumption of digital systems may increase significantly during testing. In this paper, systems equipped with a scan-based built-in self-test like the STUMPS architecture a...
126
click to vote
APWEB
2011
Springer
14 years 4 months ago
2011
Springer
This paper proposes a paraconsistent and nonmonotonic extension of description logic by planting a nonmonotonic mechanism called minimal inconsistency in paradoxical description lo...