704 search results - page 92 / 141 » On-chip logic minimization |
ACSAC
2003
IEEE
15 years 3 months ago
2003
IEEE
In-depth analysis of network security vulnerability must consider attacker exploits not just in isolation, but also in combination. The general approach to this problem is to comp...
PDP
2003
IEEE
15 years 3 months ago
2003
IEEE
As general-purpose parallel computers are increasingly being used to speed up different VLSI applications, the development of parallel algorithms for circuit testing, logic minimi...
MICRO
1998
IEEE
15 years 2 months ago
1998
IEEE
Clustering is one solution to the demand for wideissue machines and fast clock cycles because it allows for smaller, less ported register files and simpler bypass logic while rema...
ASPDAC
1998
ACM
15 years 2 months ago
1998
ACM
—An AND-OR-EXOR network, where the output EXOR gate has only two inputs, is one of the simplest three-level architecture. This network realizes an EXOR of two sum-of-products exp...
DAC
1997
ACM
15 years 2 months ago
1997
ACM
We describe an architectural design space exploration methodology that minimizes the energy dissipation of digital circuits. The centerpiece of our methodology is a Verilog-based ...