Abstract— Power dissipation has constrained the performance boosting of modern computer systems in the past decade. Dynamic power management (DPM) has been implemented in many sy...
Kai Huang, Luca Santinelli, Jian-Jia Chen, Lothar ...
Consider a multiclass stochastic network with state dependent service rates and arrival rates describing bandwidth-sharing mechanisms as well as admission control and/or load bala...
Traditionally, cache coherence in large-scale shared-memory multiprocessors has been ensured by means of a distributed directory structure stored in main memory. In this way, the ...
We consider the design of linear precoding filters with respect to the minimum mean square error (MMSE) criterion for systems that employ an additional scalar gain next to a fix...
This paper presents LOTTERYBUS, a novel high-performance communication architecture for system-on-chip (SoC) designs. The LOTTERYBUS architecture was designed to address the follo...