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ICS
1998
Tsinghua U.
15 years 7 months ago
Load Execution Latency Reduction
In order to achieve high performance, contemporary microprocessors must effectively process the four major instruction types: ALU, branch, load, and store instructions. This paper...
Bryan Black, Brian Mueller, Stephanie Postal, Ryan...
IPPS
1997
IEEE
15 years 7 months ago
A Tool for On-line Visualization and Interactive Steering of Parallel HPC Applications
Tools for parallel systems today range from specification over debugging to performance analysis and more. Typically, they help the programmers of parallel algorithms from the ea...
Sabine Rathmayer
PPOPP
1997
ACM
15 years 7 months ago
LoPC: Modeling Contention in Parallel Algorithms
Parallel algorithm designers need computational models that take first order system costs into account, but are also simple enough to use in practice. This paper introduces the L...
Matthew Frank, Anant Agarwal, Mary K. Vernon
ICPP
1993
IEEE
15 years 7 months ago
Scalability Study of the KSR-1
Scalability of parallel architectures is an interesting area of current research. Shared memory parallel programming is attractive stemming from its relative ease in transitioning...
Umakishore Ramachandran, Gautam Shah, Ravi Kumar, ...
CONCUR
1992
Springer
15 years 7 months ago
On the Semantics of Petri Nets
Petri Place/Transition (PT) nets are one of the most widely used models of concurrency. However, they still lack, in our view, a satisfactory semantics: on the one hand the "...
José Meseguer, Ugo Montanari, Vladimiro Sas...
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