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144
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ICASSP
2011
IEEE
14 years 8 months ago
2011
IEEE
In this paper we study various chain codes, which are representations of binary image contours, in terms of their ability to compress in the best way the contour information using...
146
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IPPS
2007
IEEE
15 years 11 months ago
2007
IEEE
The rapid revolution in microprocessor chip architecture due to multicore technology is presenting unprecedented challenges to the application developers as well as system softwar...
173
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ICDCS
2010
IEEE
15 years 9 months ago
2010
IEEE
—We propose a steepest descent method to compute optimal control parameters for balancing between multiple performance objectives in stateless stochastic scheduling, wherein the ...
177
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IPPS
1999
IEEE
15 years 9 months ago
1999
IEEE
In order to extract high levels of performance from modern parallel architectures, the effective management of deep memory hierarchies is very important. While architectural advan...
177
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EUROPAR
2010
Springer
15 years 6 months ago
2010
Springer
Abstract. Traditional parallel programming methodologies for improving performance assume cache-based parallel systems. However, new architectures, like the IBM Cyclops-64 (C64), b...