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ICCD
2001
IEEE
121views Hardware» more  ICCD 2001»
15 years 6 months ago
Determining Schedules for Reducing Power Consumption Using Multiple Supply Voltages
Dynamic power is the main source of power consumption in CMOS circuits. It depends on the square of the supply voltage. It may significantly be reduced by scaling down the supply ...
Noureddine Chabini, El Mostapha Aboulhamid, Yvon S...
DAC
1996
ACM
15 years 1 months ago
Design Considerations and Tools for Low-voltage Digital System Design
Aggressive voltage scaling to 1V and below through technology, circuit, and architecture optimization has been proven to be the key to ultra low-power design. The key technology t...
Anantha Chandrakasan, Isabel Yang, Carlin Vieri, D...
ISLPED
1995
ACM
108views Hardware» more  ISLPED 1995»
15 years 1 months ago
Electroid-oriented adiabatic switching circuits
A dual-rail CMOS adiabatic switching circuit approach is described which follows the electroid model of Hall. These circuits can operate in either the retractile cascade or the re...
David J. Frank, Paul M. Solomon
DATE
2005
IEEE
128views Hardware» more  DATE 2005»
15 years 3 months ago
Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits
Nanometer circuits are becoming increasingly susceptible to soft-errors due to alpha-particle and atmospheric neutron strikes as device scaling reduces node capacitances and suppl...
Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhij...
ICCD
2002
IEEE
93views Hardware» more  ICCD 2002»
15 years 6 months ago
Impact of Scaling on the Effectiveness of Dynamic Power Reduction Schemes
Power is considered to be the major limiter to the design of more faster and complex processors in the near future. In order to address this challenge, a combination of process, c...
David Duarte, Narayanan Vijaykrishnan, Mary Jane I...