Sciweavers

2652 search results - page 70 / 531
» Optimal design in collaborative design network
Sort
View
ITNG
2007
IEEE
16 years 10 days ago
On Design and Analysis of a Feasible Network-on-Chip (NoC) Architecture
In this paper, we present several enhanced network techniques which are appropriate for VLSI implementation and have reduced complexity, high throughput, and simple routing algori...
Jun Ho Bahn, Seung Eun Lee, Nader Bagherzadeh
SLIP
2006
ACM
16 years 2 days ago
Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture
— The increasing gap between design productivity and chip complexity and the emerging Systems-On-Chip (SOC) architectural template have led to the wide utilization of reusable ha...
Jin Guo, Antonis Papanikolaou, Pol Marchal, Franck...
CCR
2002
111views more  CCR 2002»
15 years 6 months ago
A taxonomy and design considerations for Internet accounting
Economic principles are increasingly being suggested for addressing some complex issues related to distributed resource allocation for QoS (Quality of Service) enhancement. Many p...
Michel Kouadio, Udo W. Pooch
IUI
2005
ACM
15 years 11 months ago
Interfaces for networked media exploration and collaborative annotation
In this paper, we present our efforts towards creating interfaces for networked media exploration and collaborative annotation. The problem is important since online social networ...
Preetha Appan, Bageshree Shevade, Hari Sundaram, D...
ISCA
2008
IEEE
170views Hardware» more  ISCA 2008»
16 years 16 days ago
Polymorphic On-Chip Networks
As the number of cores per die increases, be they processors, memory blocks, or custom accelerators, the on-chip interconnect the cores use to communicate gains importance. We beg...
Martha Mercaldi Kim, John D. Davis, Mark Oskin, To...