379 search results - page 56 / 76 » Optimal loop parallelization for maximizing iteration-level ... |
110
Voted
ICCAD
2005
IEEE
16 years 7 days ago
2005
IEEE
— One of the critical goals in code optimization for MPSoC architectures is to minimize the number of off-chip memory accesses. This is because such accesses can be extremely cos...
136
Voted
MIDDLEWARE
2009
Springer
15 years 10 months ago
2009
Springer
Abstract. The trend towards cloud and utility computing infrastructures raises challenges not only for application development, but also for management: diverse resources, changing...
117
Voted
HPDC
2007
IEEE
15 years 9 months ago
2007
IEEE
This paper describes a novel approach to generate an optimized schedule to run threads on distributed shared memory (DSM) systems. The approach relies upon a binary instrumentatio...
133
Voted
ICDCS
2007
IEEE
15 years 9 months ago
2007
IEEE
A fundamental problem in a large scale decentralized stream processing system is how to best utilize the available resources and admission control the bursty and high volume input...
234
Voted
PROCEDIA
2011
14 years 6 months ago
2011
Two decades of microprocessor architecture driven by quantitative 90/10 optimization has delivered an extraordinary 1000-fold improvement in microprocessor performance, enabled by...