8 search results - page 1 / 2 » Optimal partitioned fault-tolerant bus layout for reducing p... |
ISPD
2006
ACM
14 years 6 days ago
2006
ACM
DATE
2009
IEEE
13 years 10 months ago
2009
IEEE
Nanometer CMOS scaling has resulted in greatly increased circuit variability, with extremely adverse consequences on design predictability and yield. A number of recent works have...
ASPDAC
2006
ACM
14 years 7 days ago
2006
ACM
- Traditionally, minimum possible area of a VLSI layout is considered the best for delay and power minimization due to decreased interconnect capacitance. This paper shows however ...
CODES
2004
IEEE
13 years 10 months ago
2004
IEEE
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...
DAC
1999
ACM
13 years 10 months ago
1999
ACM
As the CMOS technology enters the deep submicron design era, the lateral inter-wire coupling capacitance becomes the dominant part of load capacitance and makes RC delay on the bu...