862 search results - page 43 / 173 » Optimal task placement to improve cache performance |
FAST
2003
14 years 11 months ago
2003
Current disk arrays, the basic building blocks of highperformance storage systems, are built around two memory technologies: magnetic disk drives, and non-volatile DRAM caches. Di...
ICCAD
2003
IEEE
15 years 3 months ago
2003
IEEE
This paper proposes for latency insensitive systems a performance optimization technique called channel buffer queue sizing, which is performed after relay station insertion in th...
VLSID
1999
IEEE
15 years 2 months ago
1999
IEEE
Interconnect tuning and repeater insertion are necessary to optimize interconnectdelay, signalperformanceandintegrity, andinterconnectmanufacturability and reliability. Repeater i...
CHI
2006
ACM
15 years 10 months ago
2006
ACM
In many environments, it is often the case that input is made to displays that are positioned non-traditionally relative to one or more users. This typically requires users to per...
CASES
2010
ACM
14 years 7 months ago
2010
ACM
Dynamic binary translators (DBTs) are becoming increasingly important because of their power and flexibility. However, the high memory demands of DBTs present an obstacle for all ...