862 search results - page 53 / 173 » Optimal task placement to improve cache performance |
FPGA
2010
ACM
15 years 6 months ago
2010
ACM
Deep submicron processes have allowed FPGAs to grow in complexity and speed. However, such technology scaling has caused FPGAs to become more susceptible to the effects of process...
ICCD
2006
IEEE
15 years 6 months ago
2006
IEEE
— The influence of interconnects on processor performance and cost is becoming increasingly pronounced with technology scaling. In this paper, we present a fast compression sche...
MICRO
2009
IEEE
15 years 4 months ago
2009
IEEE
3D-integration is a promising technology to help combat the “Memory Wall” in future multi-core processors. Past work has considered using 3D-stacked DRAM as a large last-level...
GRAPHICSINTERFACE
2011
14 years 1 months ago
2011
We present the design and experimental evaluation of pop-up depth views, a novel interaction technique for aiding in the placement or positioning of a 3D cursor or object. Previou...
CLUSTER
2008
IEEE
15 years 4 months ago
2008
IEEE
—Divisible load model allows scheduling algorithms that give nearly optimal makespan with practical computational complexity. Beaumont et al. have shown that their algorithm prod...