862 search results - page 79 / 173 » Optimal task placement to improve cache performance |
IPPS
2007
IEEE
15 years 4 months ago
2007
IEEE
— We consider memory subsystem optimizations for improving the performance of sparse scientific computation while reducing the power consumed by the CPU and memory. We first co...
IPPS
2006
IEEE
15 years 3 months ago
2006
IEEE
In this paper we study the performance improvements and trade-offs derived from an optimized mapping approach applied on a parametric coarse grained reconfigurable array architect...
CODES
2005
IEEE
15 years 3 months ago
2005
IEEE
High performance microprocessors are designed with generalpurpose applications in mind. When it comes to embedded applications, these architectures typically perform controlintens...
SIGARCH
2008
14 years 9 months ago
2008
1 This paper presents a simple but effective method to reduce on-chip access latency and improve core isolation in CMP Non-Uniform Cache Architectures (NUCA). The paper introduces ...
100
click to vote
IPPS
2009
IEEE
15 years 4 months ago
2009
IEEE
Partitioned Global Address Space (PGAS) languages provide a unique programming model that can span shared-memory multiprocessor (SMP) architectures, distributed memory machines, o...