894 search results - page 38 / 179 » Optimizations for LTL Synthesis |
104
click to vote
ISLPED
2009
ACM
15 years 5 months ago
2009
ACM
Many techniques for power management employed in advanced RTL synthesis tools rely explicitly or implicitly on observability don’t-care (ODC) conditions. In this paper we presen...
ICCAD
2005
IEEE
15 years 4 months ago
2005
IEEE
— This paper presents an architecture and a wrapper synthesis approach for the design of multi-clock systems-on-chips. We build upon the initial work on multi-clock latency-insen...
ICCAD
2000
IEEE
15 years 3 months ago
2000
IEEE
— Memory is one of the most important components to be optimized in the several phases of the synthesis process. ioral synthesis, a memory is viewed as an abstract construct whic...
ICCAD
1998
IEEE
15 years 3 months ago
1998
IEEE
We present a method for optimizing and automating component and transistor sizing for CMOS operational amplifiers. We observe that a wide variety of performance measures can be fo...
DAC
2005
ACM
15 years 29 days ago
2005
ACM
This paper presents a novel synthesis algorithm that reduces the area needed for implementing multiplexers on an FPGA by an average of 18%. This is achieved by reducing the number...