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» Optimizations for LTL Synthesis
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ICCAD
2002
IEEE
113views Hardware» more  ICCAD 2002»
15 years 8 months ago
Interconnect-aware high-level synthesis for low power
Abstract—Interconnects (wires, buffers, clock distribution networks, multiplexers and busses) consume a significant fraction of total circuit power. In this work, we demonstrat...
Lin Zhong, Niraj K. Jha
FPGA
2009
ACM
154views FPGA» more  FPGA 2009»
15 years 5 months ago
Synthesis of reconfigurable high-performance multicore systems
Reconfigurable high-performance computing systems (RHPC) have been attracting more and more attention over the past few years. RHPC systems are a promising solution for accelerati...
Jason Cong, Karthik Gururaj, Guoling Han
ISSS
2000
IEEE
127views Hardware» more  ISSS 2000»
15 years 3 months ago
Lower Bound Estimation for Low Power High-Level Synthesis
This paper addresses the problem of estimating lower bounds on the power consumption in scheduled data flow graphs with a fixed number of allocated resources prior to binding. T...
Lars Kruse, Eike Schmidt, Gerd Jochens, Ansgar Sta...
CORR
2010
Springer
53views Education» more  CORR 2010»
14 years 11 months ago
Phase-Only Planar Antenna Array Synthesis with Fuzzy Genetic Algorithms
This paper describes a new method for the synthesis of planar antenna arrays using fuzzy genetic algorithms (FGAs) by optimizing phase excitation coefficients to best meet a desir...
Boufeldja Kadri, Miloud Boussahla, Fethi Tarik Ben...
DATE
2008
IEEE
114views Hardware» more  DATE 2008»
15 years 5 months ago
Synthesis of Fault-Tolerant Embedded Systems
This work addresses the issue of design optimization for faulttolerant hard real-time systems. In particular, our focus is on the handling of transient faults using both checkpoin...
Petru Eles, Viacheslav Izosimov, Paul Pop, Zebo Pe...