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» Optimizing Compilation of CLP(R)
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DAC
2007
ACM
15 years 10 months ago
Chip Multi-Processor Generator
The drive for low-power, high performance computation coupled with the extremely high design costs for ASIC designs, has driven a number of designers to try to create a flexible, ...
Alex Solomatnikov, Amin Firoozshahian, Wajahat Qad...
DAC
2007
ACM
15 years 10 months ago
A Self-Tuning Configurable Cache
The memory hierarchy of a system can consume up to 50% of microprocessor system power. Previous work has shown that tuning a configurable cache to a particular application can red...
Ann Gordon-Ross, Frank Vahid
DAC
2002
ACM
15 years 10 months ago
An energy saving strategy based on adaptive loop parallelization
In this paper, we evaluate an adaptive loop parallelization strategy (i.e., a strategy that allows each loop nest to execute using different number of processors if doing so is be...
Ismail Kadayif, Mahmut T. Kandemir, Mustafa Karak&...
DAC
2005
ACM
15 years 10 months ago
Towards scalable flow and context sensitive pointer analysis
Pointer analysis, a classic problem in software program analysis, has emerged as an important problem to solve in design automation, at a time when complex designs, specified in t...
Jianwen Zhu
ICSE
2009
IEEE-ACM
15 years 10 months ago
The road not taken: Estimating path execution frequency statically
A variety of compilers, static analyses, and testing frameworks rely heavily on path frequency information. Uses for such information range from optimizing transformations to bug ...
Raymond P. L. Buse, Westley Weimer