— We consider memory subsystem optimizations for improving the performance of sparse scientific computation while reducing the power consumed by the CPU and memory. We first co...
We consider the problem of performance driven lookup-table (LUT) based technology mapping for FPGAs using a general delay model. In the general delay model, each interconnection e...
We propose efficient scheduling algorithms for downlink MIMO-CDMA systems using zero forcing beamforming to achieve high system throughput with low computational complexity. Base...
We improve the approximation ratios for two optimization problems in planar graphs. For node-weighted Steiner tree, a classical network-optimization problem, the best achievable ap...
Erik D. Demaine, MohammadTaghi Hajiaghayi, Philip ...
This paper proposes for latency insensitive systems a performance optimization technique called channel buffer queue sizing, which is performed after relay station insertion in th...