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EUROPAR
1997
Springer
15 years 6 months ago
Modulo Scheduling with Cache Reuse Information
Instruction scheduling in general, and software pipelining in particular face the di cult task of scheduling operations in the presence of uncertain latencies. The largest contrib...
Chen Ding, Steve Carr, Philip H. Sweany
ICS
1999
Tsinghua U.
15 years 6 months ago
Software trace cache
—This paper explores the use of compiler optimizations which optimize the layout of instructions in memory. The target is to enable the code to make better use of the underlying ...
Alex Ramírez, Josep-Lluis Larriba-Pey, Carl...
GECCO
2004
Springer
15 years 7 months ago
Improving the Performance of a Genetic Algorithm Using a Variable-Reordering Algorithm
Genetic algorithms have been successfully applied to many difficult problems but there have been some disappointing results as well. In these cases the choice of the internal repre...
Eduardo Rodriguez-Tello, Jose Torres-Jimenez
DAC
2007
ACM
16 years 3 months ago
A Self-Tuning Configurable Cache
The memory hierarchy of a system can consume up to 50% of microprocessor system power. Previous work has shown that tuning a configurable cache to a particular application can red...
Ann Gordon-Ross, Frank Vahid
GECCO
2003
Springer
15 years 7 months ago
A Kernighan-Lin Local Improvement Heuristic That Solves Some Hard Problems in Genetic Algorithms
We present a Kernighan-Lin style local improvement heuristic for genetic algorithms. We analyze the run-time cost of the heuristic. We demonstrate through experiments that the heur...
William A. Greene