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» Optimizing Logic Design Using Boolean Transforms
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TCAD
2008
92views more  TCAD 2008»
14 years 9 months ago
IP Watermarking Using Incremental Technology Mapping at Logic Synthesis Level
Abstract--This paper proposes an adaptive watermarking technique by modulating some closed cones in an originally optimized logic network (master design) for technology mapping. Th...
Aijiao Cui, Chip-Hong Chang, Sofiène Tahar
DAC
2007
ACM
15 years 1 months ago
Skewed Flip-Flop Transformation for Minimizing Leakage in Sequential Circuits
Mixed Vt has been widely used to control leakage without affecting circuit performance. However, current approaches target the combinational circuits even though sequential elemen...
Jun Seomun, Jaehyun Kim, Youngsoo Shin
ICDE
2007
IEEE
145views Database» more  ICDE 2007»
15 years 11 months ago
Fast Identification of Relational Constraint Violations
Logical constraints, (e.g., 'phone numbers in toronto can have prefixes 416, 647, 905 only'), are ubiquitous in relational databases. Traditional integrity constraints, ...
Amit Chandel, Nick Koudas, Ken Q. Pu, Divesh Sriva...
GLVLSI
2007
IEEE
171views VLSI» more  GLVLSI 2007»
15 years 4 months ago
Combinational equivalence checking for threshold logic circuits
Threshold logic is gaining prominence as an alternative to Boolean logic. The main reason for this trend is the availability of devices that implement these circuits efficiently (...
Tejaswi Gowda, Sarma B. K. Vrudhula, Goran Konjevo...
LOPSTR
2004
Springer
15 years 3 months ago
Determinacy Analysis for Logic Programs Using Mode and Type Information
We propose an analysis for detecting procedures and goals that are deterministic (i.e. that produce at most one solution), or predicates whose clause tests are mutually exclusive (...
Pedro López-García, Francisco Bueno,...