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» Optimizing Technology Mapping for FPGAs Using CAMs
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71
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FPGA
2004
ACM
137views FPGA» more  FPGA 2004»
15 years 2 months ago
Making visible the thermal behaviour of embedded microprocessors on FPGAs: a progress report
This paper shows a method to verifying the thermal status of complex FPGA-based circuits like microprocessors. Thus, the designer can evaluate if a particular block is working bey...
Sergio López-Buedo, Eduardo I. Boemo
DAC
1996
ACM
15 years 1 months ago
Delay Minimal Decomposition of Multiplexers in Technology Mapping
Technology mapping requires the unmapped logic network to be represented in terms of base functions, usually two-input NORs and inverters. Technology decomposition is the step tha...
Shashidhar Thakur, D. F. Wong, Shankar Krishnamoor...
87
Voted
FPL
1997
Springer
242views Hardware» more  FPL 1997»
15 years 1 months ago
Technology mapping by binate covering
Technology mapping can be viewed as the optimization problem of finding a minimum cost cover of the given Boolean network by choosing from given library of logic cells. The core of...
Michal Servít, Kang Yi
ICCAD
2008
IEEE
138views Hardware» more  ICCAD 2008»
15 years 6 months ago
Fault tolerant placement and defect reconfiguration for nano-FPGAs
—When manufacturing nano-devices, defects are a certainty and reliability becomes a critical issue. Until now, the most pervasive methods used to address reliability, involve inj...
Amit Agarwal, Jason Cong, Brian Tagiku
MICRO
2010
IEEE
173views Hardware» more  MICRO 2010»
14 years 7 months ago
Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?
To extend the exponential performance scaling of future chip multiprocessors, improving energy efficiency has become a first-class priority. Single-chip heterogeneous computing ha...
Eric S. Chung, Peter A. Milder, James C. Hoe, Ken ...