2703 search results - page 327 / 541 » Optimizing memory transactions |
149
Voted
GLVLSI
2005
IEEE
15 years 9 months ago
2005
IEEE
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
152
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MM
2003
ACM
15 years 9 months ago
2003
ACM
Optimizing user experience for streaming video applications on handheld devices is a significant research challenge. In this paper, we propose an integrated power management appr...
144
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PLDI
2011
ACM
14 years 6 months ago
2011
ACM
The most intuitive memory consistency model for shared-memory multi-threaded programming is sequential consistency (SC). However, current concurrent programming languages support ...
144
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DAC
2007
ACM
16 years 5 months ago
2007
ACM
The memory hierarchy of a system can consume up to 50% of microprocessor system power. Previous work has shown that tuning a configurable cache to a particular application can red...
142
Voted
TACAS
2009
Springer
15 years 10 months ago
2009
Springer
Software testing is an essential process to improve software quality in practice. Researchers have proposed several techniques to automate parts of this process. In particular, sym...