2703 search results - page 418 / 541 » Optimizing memory transactions |
130
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IPPS
2009
IEEE
15 years 10 months ago
2009
IEEE
PDE solvers using Adaptive Mesh Refinement on block structured grids are some of the most challenging applications to adapt to massively parallel computing environments. We descr...
125
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CLUSTER
2008
IEEE
15 years 10 months ago
2008
IEEE
—The increasing performance and decreasing cost of processors and memory are causing system intelligence to move from the CPU to peripherals such as disk drives. Storage system d...
140
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ICPP
2008
IEEE
15 years 9 months ago
2008
IEEE
This paper presents a novel stateless, virtualized communication engine for sub-microsecond latency. Using a Field-Programmable-Gate-Array (FPGA) based prototype we show a latency...
150
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ISCA
2008
IEEE
15 years 9 months ago
2008
IEEE
As the number of cores per die increases, be they processors, memory blocks, or custom accelerators, the on-chip interconnect the cores use to communicate gains importance. We beg...
114
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CGO
2007
IEEE
15 years 9 months ago
2007
IEEE
Memory transfers are becoming more important to optimize, for both performance and power consumption. With this goal in mind, new register allocation schemes are developed, which ...