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» Optimizing pipelines for power and performance
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ISCA
2011
IEEE
287views Hardware» more  ISCA 2011»
14 years 5 months ago
Scalable power control for many-core architectures running multi-threaded applications
Optimizing the performance of a multi-core microprocessor within a power budget has recently received a lot of attention. However, most existing solutions are centralized and cann...
Kai Ma, Xue Li, Ming Chen, Xiaorui Wang
113
Voted
IEEEINTERACT
2003
IEEE
15 years 7 months ago
High Performance Code Generation through Lazy Activation Records
For call intensive programs, function calls are major bottlenecks during program execution since they usually force register contents to be spilled into memory. Such register to m...
Manoranjan Satpathy, Rabi N. Mahapatra, Siddharth ...
133
Voted
PLDI
2009
ACM
15 years 8 months ago
Proving optimizations correct using parameterized program equivalence
Translation validation is a technique for checking that, after an optimization has run, the input and output of the optimization are equivalent. Traditionally, translation validat...
Sudipta Kundu, Zachary Tatlock, Sorin Lerner
CASES
2007
ACM
15 years 5 months ago
A low power front-end for embedded processors using a block-aware instruction set
Energy, power, and area efficiency are critical design concerns for embedded processors. Much of the energy of a typical embedded processor is consumed in the front-end since inst...
Ahmad Zmily, Christos Kozyrakis
154
Voted
INFOCOM
2007
IEEE
15 years 8 months ago
Distributed Relay Selection and Power Control for Multiuser Cooperative Communication Networks Using Buyer/Seller Game
— The performances in cooperative communications depend on careful resource allocation such as relay selection and power control, but traditional centralized resource allocation ...
Beibei Wang, Zhu Han, K. J. Ray Liu